Memory controllers are designed to interface to various types of memory, on behalf of one or more requesters (e.g. processors, peripheral devices, etc.). Typically, a memory controller is designed to provide certain latency and bandwidth characteristics. In general, it is desirable to provide low latency and high bandwidth access to memory. However, it is frequently the case that optimizations made to reduce latency may reduce the bandwidth.
Similarly, it is frequently the case that optimizations made to increase the bandwidth lead to increased latency. Thus, the designer must often make choices between low latency features and high bandwidth features in designing a memory controller.
The latency and bandwidth characteristics of a given memory controller may be selected, e.g., based on the expected workload of the memory controller. For example, memory controllers may often be optimized for processor accesses, in which latency is often the key characteristic. Other types of workloads may favor bandwidth over latency. For example, in networking environments, large numbers of packets may be written to and read from memory. While low latency for such accesses is desirable, having high bandwidth may be more important to ensure that the packets can be written to and read from memory without having to drop packets, or without slowing down the network packet traffic with flow control.
Reference is made to FIG. 1, which is a block diagram of certain components that illustrate a manner in which devices on a system bus are interfaced with external memory, in a manner that is known in the prior art. For purposes of simplicity, and better illustrating inventive features (by later reference to a comparative diagram of an inventive embodiment), labels and designators for certain devices have been genericized. For example, the diagram of FIG. 1 illustrates an “External Interface” 10, which is coupled to “External Memory” 12. The external interface 10 could be a memory controller, or alternatively could be another device or circuit (e.g., a specialized circuit) for interfacing with memory 12.
As is known, a system bus 20 may be configured to accommodate a number of devices, including a plurality of master devices 22, 24, and 26. In this regard, a master device generically refers to a device that is configured to be capable of assuming control of driving the system bus 20. That is, any device that can assume “mastery” of communications over the system bus 20, at any given time. As an example, a system bus 20 may be coupled to a large number of devices including multiple, independent processors, DMA controllers, print servers, and other devices. At any given time, any of these devices may be responsible for controlling the information that is placed on the system bus 20. Arbitration logic (not specifically shown) is provided to arbitrate the control over the bus 20, so that only one device has mastery or control of the system bus 20 at any given time. This concept and operation is well known, and need not be described herein.
As is also known, the various master devices 22, 24, and 26 may, at times, communicate information with external memory 12. A bus interface (in the form of circuitry and/or logic) 30 is provided to interface the system bus 20 with external memory 12, or as illustrated in FIG. 1, with the external interface 10. Therefore, information communicated from, for example, Master N 26 to external memory 12 is first communicated through bus interface 30, then external interface 10 (which may be a memory controller), then on to external memory 12.
As is further known, communication flow between bus interface 30 and external memory 12 is further enhanced by buffers 40 and 45, which are interposed between the bus interface 30 and external memory 12 (or in the illustrated embodiment, between bus interface 30 and external interface 10). In known systems, certain buffers 40 are designed as read buffers. Data is placed in read buffers 40 when it is sent from external memory 12 to a requesting master device. In this respect, when a master device issues a request to “read” data from external memory, the data is communicated from the external memory 12 to the bus interface 30 via read buffers 40. Likewise, when a master device issues a “write” instruction, to write data from the system bus 20 into external memory 12, such data is first communicated through write buffers 45. In situations where multiple data items are read or written in relatively immediate succession, the utilization of buffers 40 and 45 enhances the speed (and therefore data flow) of these operations.
As an example, consider a situation in which master 22 issues three consecutive write instructions to write data into external memory 12. Without the buffers, the first item of data would be passed through bus interface 30, external interface 10, and written to external memory 12. After the data was written into external memory 12, a confirmation indication would be passed back to the master 22, and after receiving this confirmation, the master would then initiate the write of the next item of data. In contrast, in systems employing write buffers 45, the master may, in virtually immediate succession, write all three items of data into write buffers 45. Thereafter, the external interface 10 and memory 12 will receive the data items. Writing data in this fashion greatly expedites the flow and allows the master 22 to relinquish the system bus 20, such that it is more accessible and available to other master devices coupled to the bus 20. A similar efficiency is gained through the implementation of read buffers 40. As such systems and circuits are well known, further detailed discussion need not be provided herein.
Although these circuits provide certain performance and operational enhancements, they do suffer from various shortcomings. For example, consider a situation in which master 22 issues three consecutive write commands to write various data items into external memory. After issuing these commands, master 22 relinquishes the bus 20. Further assume that master 24 issues a read request for data at an address that corresponds to one of the three items of data just written by master 22. Specifically, assume that the system determines that the data requested by master 24 is presently in a write buffer 45. Address comparison logic 50 is provided to make this determination, and through signaling provided via the bus interface 30, master 24 is instructed to wait for this data (as it is not yet available). Instead, the master 24 has to wait until the data is written from the respective write buffer 45 through the external interface 10 into external memory, before it is “available” to be read by master 24.
The forgoing is merely one illustration of a situation in which further performance enhancements are desired from the systems known in the prior art. Therefore, there is a desire for this and other enhancements to be made to systems known in the prior art.